`timescale 1ns / 1ps

module main(MAIN_CLK, LINK_OK,
			  S_CLK, S_DATA,			
			);
			
 
wire[31:0]data_in_1;
wire[31:0]data_in_2;
wire[31:0]data_in_3;
wire[31:0]data_in_4;

reg[31:0]data_out_1;
reg[31:0]data_out_2;
reg[31:0]data_out_3;
reg[31:0]data_out_4;



A_sp_slave #(`DEV_ID, `PAUSE) sp(
          MAIN_CLK, 
		  linkOk,
		  en_out,
		  S_CLK,
		  S_DATA,
		  data_in_1, data_in_2, data_in_3, data_in_4, cmd_in,
		  data_out_1, data_out_2, data_out_3, data_out_4, cmd_out
		);

   

endmodule